Hi team,
Here's an issue from the customer may need your help:
The CRL6 is set to 0x0F, and the stall detection is on to detect the out-of-step status bit of the failure status (address 0x00).
At the beginning of the power-on test, the test is normal several times (simulated with stall). However, after several operations (the number of times is not fixed), a failure to detect a step is encountered. The value for a real-time read of CTRL7 is less than the value set by CTRL6 and the read of CTRL5 EN_STL bit is 1, meaning that the detection is enabled, but the failure condition cannot be set.
The red dash is the SPI read address 02 status data (16 bits). Fault-free can be seen according to the IC definition. And the blue dash is the data for address 9 and address 8 is set to 15. It can be seen that many times the data was less than the set value during stall, but the SPI read of address 02 status data (16 bits) did not have the corresponding status.
The command to clear the fault condition sometimes detects a stall correctly, but sometimes it does not.
As described below, a value of CTRL7 below the value set by CTRL6 sets the out-of-step status bit (the out-of-step detection is enabled), but the actual test looks like this.
Could you help check this case? Thanks.
Best Regards,
Cherry
