DRV8894 the register of sense signal for the transfer

Hi all

Would you mind if we ask DRV8894?

<Question1>
In case of SXLD=Low, logic level of SSOUT and SP1 are the same.
Is it correct operation?

<Question2>
In relation to <Question1>, if this is correct operation, why will SSOUT and SP1 become the same logic level?
Our customer would like to know internal operating principles.
We could not find these contents on the datasheet.
Especially there is no truth table and timing chart.

Kind regards,

Hirotaka Matsumoto