Part Number:DRV8704
Hello,
I was wondering if the support team could offer some advice on a design where we are implementing the DRV8704 into a TEC (Peltier) driver system. To achieve this, the outputs (xOUT1 and xOUT2) from the MOSFET bridge are LC low-pass filtered (yet to be optimised). Depending on the complementary duty cycle of the PWM inputs to the DRV8704 (an inverter is used on a single PWM signal to provide true commentary inputs), the DC output has a bipolar swing from 0V differential voltage through to almost the full VM (PVIN: +48V) across the outputs. So, each output will have ½ of VM applied to it for a 50/50 duty cycle into the device. The MCU is not generating the PWM signals but has control over if they are in-phase or are inverted, and if they get sent to the DRV8704 or not (can be disabled).
I have attached schematic captures of the DRV8704 driver, bridge, and output filters. The SLEEPn line can be assumed to always be pulled high in fixed hardware, the RESET line is controlled by an MCU (internal pullup enabled), however currently this has no external pullup on. I am aware the DRV8704 has an internal pulldown on this pin. The PCB layout is fashioned as the one recommended in the datasheet. I have a six-layer PCB where the gate drive traces via straight from the device pins into an internal layer and are widened.
I have a prototype board where I have implemented this circuit. Sometimes the DRV8704 asserted it’s FAULTn pin upon power-up (applying VM and applying +3V3 to SLEEPn). I didn’t get chance to read the status register unfortunately. The device and the four MOSFETs died after only a very small amount of testing was completed. It seems the driver chip has popped a hole in its plastic casing, close to the charge pump area / HS drive. The four MOSFETs have also died, however I am not sure if it was the FETs that killed the driver or the driver that took out the FETs (I assume the latter). The driver was using all default register settings at the time, with a PWM input frequency of 200kHz. A 10-ohm load was connected across the outputs at the time. Initially I assumed a shoot-through event, however the MOSFETs seems to mainly have failed from a gate-source over-voltage (almost as if the full VM has been applied to them):
Q7: G-S short.
Q8: G-S short.
Q10: G-S short. D-S short.
Q9: G-S short. 1k D-S.
My first question is, can you clarify the safest way to boot the driver up as the datasheet doesn’t seem to give this information. I assume that VM should first be applied, with the device held in SLEEPn and RESET (to make sure the H-bridge is disabled). The fact that both SLEEPn and RESET have internal pulldowns suggest that it is safe for the device to power up out of reset mode. When my device died, I had the following procedure:
- Boot up (apply VM), SLEEPn pulled to +3V3.
- Pull RESET line low (so device is awake, charge pump is active, and device is waiting for PWM inputs).
- Wait two seconds.
- Send complementary PWM inputs to AIN1 and AIN2.
I can’t be sure what the duty-cycle of the PWM inputs were at the time, but I am relatively confident the device died AFTER the two second wait. I think the device needs a strong pullup on the RESET line, so the device doesn’t bounce around when the MCU is programmed etc; I suspect this could damage the drivers and FETs. Could it be of any danger to provide large differences in duty-cycle to the inputs while the device is brought out of reset? Could the device or MOSFETs be at risk if the RESET pin is toggled while PWM is still being applied to the inputs (for example would the OCP circuitry still be active during the RESET toggle?).
I can’t see any obvious issues in driving the CSD19531Q5A FETs with the default register setup, even at 200kHz. I think it may be wise to change the VCP capacitor from a 16V to say a 50V capacitor however. Or it could be possible that the LC filtering itself had something to do with the failure.
I've also attached a scope capture of the driver driving the four FETs (on a different board before this fault was experienced). Does the charged-pumped rise time look normal on the HS outputs (around 200ns for the ~12V charge pump voltage to driver the HS FETs).
Apologies for the quantity of questions and the long post, but there may be something obvious that I am missing here.
Thank you for any advice that can be offered.
Kind Regards,
Stephen
