Part Number:DRV8308
I am currently using the DRV8308 to drive a BLDC motor with three SIZ342DT-T1-GE3 dual NMOS drivers. I am trying to maximize the amount of torque (and therefore power) delivered to the motor when it becomes stalled to allow it "push past" any obstructions or friction it may encounter. A current limit and the UVLO fault flag are used to stop the motor if it becomes apparent the motor cannot continue moving with a reasonable amount of power.
The problem I encountered was this: When stalling a motor with a vice, at a 50 kHz FET output frequency, the duty cycle of the FET output was limited to 30% when using a CLKIN duty cycle of anything above 30%. With CLKIN duty cycles lower than 30%, the output duty cycle matched it as expected. While changing settings, I noticed that a change of output frequency to 200 kHz (with no additional changes) allows the FET output duty cycle to continue to rise to match that of CLKIN until an overcurrent or UVLO condition is met. This behavior is the same in open loop or closed loop speed control for both output PWM settings. I have included pictures below of the duty cycles and power consumption of each mode below. I have also included all of my driver settings at the end of this message.
While changing the FET output frequency to 200 kHz may allow me to deliver enough power to the motor, I would like to know why the driver would limit the duty cycle of the FET switching signal when using a 50 kHz frequency. I could not find any mention of limiting in the datasheet. Is this done automatically by the driver, or could this only be an issue with the FETs or the motor? Happy to provide any additional information on my setup or configuration that will be helpful. Any help or insight into this matter would be greatly appreciated.
Thank you,
Andrew
Scope photos:
50 kHz FET PWM. CLKIN (yellow) at 68% duty cycle. HALL_U (purple) at 30% duty cycle. Current draw maxed out at 1.323 A.
200 kHz FET PWM. CLKIN (yellow) at 68% duty cycle. HALL_U (purple) at 68% duty cycle. Current draw maxed out at 3.82 A.
Driver system settings and details:
Chip: DRV8308RHAR
ISENS limit: 43 mΩ for a 5.8A current limit
Driving FETs: SIZ342DT-T1-GE3 dual NMOS package
Motor/FET voltage: 12 V
Microcontroller: STM32L432KX
Config registers:
AG_SETPT: 1001 (1.5 kHz)
ENPOL: 1
DIRPOL: 0
BRKPOL: 1
SYNRECT: 1
PWMF: 11 (200 kHz) for successful power delivery; 01 (50 kHz) to replicate this issue
SPDMODE: 01 (clock PWM)
FGSEL: 00 (HALL_U)
BRKMOD: 1
RETRY: 1
ADVANCE: 0x00
SPDREVS: 0x04
MINSPD: 0xFF
BASIC: 1
SPEEDTH: 010 (1/128 rev)
MOD120: 0x800
HALLRST: 00 (every Hall cycle)
DELAY: 0
AUTOADV: 0
AUTOGAIN: 0
ENSINE: 0
TDRIVE: 11 (15 us)
DTIME: 010 (240 ns)
IDRIVE: 010 (30 mA)
INTCLK: 000 (50 MHz)
SPDGAIN: 0x000
HALLPOL: 0
BYPFILT: 0
FILK1: 0x000
FILK2: 0x000
BYPCOMP: 0
COMK1: 0x000
AA_SETPT: 0000 (3 Hz)
COMK2: 0x000
OCPDEG: 11 (5 us, 6 us)
OCPTH: 11 (1000 mV)
OVTH: 0
VREG_EN: 0
LOOPGAIN: 0000000000 (all 10 bits = 0)