DRV8351-SEP: Question about formula (1) in the data sheet

Tool/software:

Dear TI support,

I am planning to use the DRV8351-SEP as gate drivers for two NMOS-Mosfets (DMN1017UCP3-7, with a V_GS(th) of 1.2V) in a Buck Driver configuration. My drain voltage for the high-side Mosfet is between 0.5V and 4.6V, and my G_VDD is 5V. I have an input PWM signal (high+low) operating at 350kHz. As far as I understand the internal circuitry (please correct me if I am wrong), this gate driver pumps the voltage to (0.5V...4.6V) + 5V - 0.85V, allowing the NMOS to operate properly across the input (drain) voltage range thanks to the ~4V offset.

However, when plugging these values into equation (1) in the data sheet, I get a negative value for the "allowed voltage drop across bootstrap capacitor": 

ΔV_BST = V_GVDD - V_BOOTD - V_BSTUV

= 5V - 0.85V - 4.5V = -0.35V.

If I insert this negative value in formula (3), I get a negative capacitance, which doesn't seem reasonable to me. Am I misunderstanding something? Or is the gate driver not working as I think it would, and is unsuitable for the envisioned task? What else should I use in that case to ensure (only with a 5V and a 28V rail available as supplies) and a 3V3 logic input signal operating at 350kHz that the Mosfets fully open as intended?

Thank you on behalf for your answer.