DRV8145-Q1: Confirmation that nSCS must be toggled for SPI Communication?

I recently used this chip in my first-ever PCB design.  I'm having trouble getting it to transition from INIT2 state to STANDBY.  In doing more digging, I suspect I may have found the issue but wanted to get confirmation if possible.

Because this is the only SPI device on the board, I permanently asserted the nSCS (Chip Select - Pin 2) low to save IOs on the MCU.  But I see in the datasheet that "nSCS should be pulled high between words" and now I suspect that my not having that transition could be my problem.

Can anyone confirm that a state transition on nSCS is required (or not) for SPI communication to work?

Appreciate any help!