Hello, I am currently trying to set up the DRV8462evm with the Sitara-AM437x processor over SPI. After startup I send 5 registers I want to write to, namely 0x4, 0x5, 0x6, 0xC and 0x10, as shown below. Even though the outgoing packets on the MOSI are accurate, I do not get a response from the driver. I connected the onboard evm microcontroller and looked at the SPI transactions as I controlled the driver through the TI GUI and found that my MISO line pulled low in between transactions while the onboard microcontroller had pulled the line high.
My SPI Transaction:
Close up:
Onboard MCU transaction for reference:
My MODE pin is also pulled up to logic high to use the driver in SPI mode. I am supplying 24V as VM and TP28 shows 5V being supplied to the driver itself.
Things I have already tried:
Internal Pullup for the MISO line (3.3v) - Signal was pulled to 0v as soon as CS was pulled low.
External Pullup for the MISO line (3.3V with 3.9kΩ) - Line was never pulled low and stayed at logic high throughout the transaction.
nSleep pulse between 20us and 40us before initiating the SPI transaction. No change during transaction.
Switching MISO and MOSI lines to make sure I wired the signal correctly.
Any help will be appreciated as I have no idea what else to try.
Separately, the data sheet states, "Data on SDO from the device is propagated on the rising edge of SCLK, while data on SDI is captured by the device on the subsequent falling edge of SCLK.". I have never come across a device that sends and receives data on different edges of the clock, i.e., the CPHA of SPI. How should this be handled on the microcontroller side as I can send and receive data on only one edge of the clock.
