DRV8251A: Question about OCP and voltage test.

Hi Team,

My customer is testing the DRV8251A and we have some question below, 

1.Customers are conducting reliability tests on DRV8251. They increase the VM to about 52V and find that the chip can still work normally. Customer wants to know how our 50V absolute maximum is tested.

2.The customer is testing the function of OCP, using the EVM board for testing, the simple diagram is shown in the figure below.

After the customer short-circuits OUT1 and OUT2 (the switch is closed), no action is taken. IN1, IN2 have PWM signal. We can see that after the current rises, it is quickly protected, and the current drops to 0. But I am very confused about why there are repeated protections. According to my understanding, after the OCP is triggered, the H-bridge should be locked, and it will be reset only when the power is turned on again. But from the waveform point of view, there is self-recovery. Do you have any comments on this? Is it possible that the OTSD was triggered first.

Thank you in advance for your support.

Jenson