DRV8323: About the specifications

Hi Team,

I would like to know about Figure 27 (TDRIVE State Machine) in specification DRV8323.

The input signal is not simultaneous due to the dead time of the CPU.

I think that the time difference between VINHx and VINLx is not a problem if the register setting is appropriate, but is it correct?

Also, please let us know if you have any concerns or precautions due to the time difference.

Best Regards,

Tom Liu