DRV8323: Problem with the fault signal

voidDRV8323_initRegs(DRV8323_VARS_t *v) {

   

    // Set Register Driver Control Register (0x02)

    v->Driver_Control.bits.DIS_CPUV = drv_chargePump_faultEnable; // 0

    v->Driver_Control.bits.DIS_GDF = drv_gateDrive_faultEnable; // 0

    v->Driver_Control.bits.OTW_REP = drv_otw_no_report; // 0

    v->Driver_Control.bits.PWM_MODE = drv_PWM_mode_6; // 0

    v->Driver_Control.bits.PWM_COM_1 = drv_1xPWM_synch; // 0

    v->Driver_Control.bits.PWM_DIR_1 = drv_1xPWM_noChangeDir; // 0

    v->Driver_Control.bits.COAST = drv_coastDisable; // 0

    v->Driver_Control.bits.BRAKE = drv_brakeDisable; // 0

    v->Driver_Control.bits.CLR_FLT = drv_leaveFaults; // 0

    v->Gate_Drive_HS.bits._LOCK = drv_unlock; // 3

    v->Gate_Drive_HS.bits.IDRIVEP_HS = drv_idriveP_hs_190mA; // 7

    v->Gate_Drive_HS.bits.IDRIVEN_HS = drv_idriveN_hs_380mA; // 7

    // Set Register Gate Drive LS Register (0x04)

    v->Gate_Drive_LS.bits.CBC = drv_clrFaults; // 1

    v->Gate_Drive_LS.bits.TDRIVE = drv_tdrive_4000nS; // 3

    v->Gate_Drive_LS.bits.IDRIVEP_LS = drv_idriveP_ls_190mA; // 7

    v->Gate_Drive_LS.bits.IDRIVEN_LS = drv_idriveN_ls_380mA; // 7

   

    // Set Register OCP Control Register (0x05)

    v->OCP_Control.bits.TRETRY = drv_retry_time_4ms; // 0

    v->OCP_Control.bits.DEAD_TIME = drv_deadTime_100nS; // 1

    v->OCP_Control.bits.OCP_MODE = drv_ocp_mode_reportNoAction; // 2

    v->OCP_Control.bits.OCP_DEG = drv_ocp_deg_4us; // 1

    v->OCP_Control.bits.VDS_LVL = drv_vds_lvl_260mV; // 3

    // Set Register CSA Control Register (0x06)

    v->CSA_Control.bits.CSA_FET = drv_input_SHx; // 1

    v->CSA_Control.bits.VREF_DIV = drv_vref_div_unipolar; // 0

    v->CSA_Control.bits.LS_REF = drv_vds_ocp_SHx_SNx; // 1

    v->CSA_Control.bits.CSA_GAIN = drv_gain_20; // 2

    v->CSA_Control.bits.DIS_SEN = drv_oc_faultDisable; // 1

    v->CSA_Control.bits.CSA_CAL_A = drv_normal_sense; // 0

    v->CSA_Control.bits.CSA_CAL_B = drv_normal_sense; // 0

    v->CSA_Control.bits.CSA_CAL_C = drv_normal_sense; // 0

    v->CSA_Control.bits.SEN_LVL = drv_ocp_1000mV; // 3

}

We don't have a shunt resistor on the half bridge so we are using the Vds to monitor the current. So we have set the bit DIS_SEN to disable the overcurrent fault but this doesn't seem to work as expected.

The problem is that, even if the Vds is never greater than 1V (as set with the CSA_Control bit SEN_LVL), the bit 10, 9 and 8 of the status register 2 (address 0x01) is set to 1 (the register value is 0x700) as soon as the correrspondendt half bridge is driven.