We got some customer technical question.
In DS Pg.7, we can check the timing diagram and definition of each time spec.
In 6, wake up time spec, what does it mean of this?
In sleep mode operation, sleep mode will disable when sleep pin is high. But it looks like we should input STEP signal in maximum 1ms. Should we do this?
I cannot understand its intention.
2. In 9, Disable time
Is it typo this description? IC will operate when Enable is low and disable when enable is high. Customer checked when enable is high and time to output is disable.
But in this timing diagram, I think it is different what I and customer understood and tested. What is intention of this spec?
What does Inactive high means? Active low? Or just low. It make us confused.
Regards,