DRV8307EVM: is this shoot throw or is this incorrect controls?

This is our Main Board running a DRV8307….. Below is yellow, blue, red are the three phases (line to return) and the green is one phase current.

This is TI’s EVM Board running a  DRV8307….. Below is yellow, blue, red are the three phases (line to return) and the green is one phase current.

Now: I hand drew the green current waveforms below and is my question; I drew the conducting part of the current waveforms from above; one from the main board and one from the TI EVM board.

The Main board has two peaks with a slope up and a slope down, the TI EVM board has one peak and starts a slope down and then a slope up….. is this shoot throw or is this incorrect controls?

A clearer screen capture: yellow= phase voltage, blue=low side gate of fet, red=highside gate of fet, green is the phase current…..   THE OTHER PHASES LOOK TO BE CURRENT LIMITING

BECAUSE THE HIGHSIDE GATEDRIVE VOLTAGE IS LOWER THAN THIS ONE ( 24 +10) , THIS ONE IS AT 34 VOLTS THE OTHER TWO ARE NOT…..

Screen shot of next phase lowside and highside gate voltages; high side is being voltage limited:

and the third phase;

emails:

Calvo, Matthew <m-calvo@ti.com>

McKay, Scott <Scott.Mckay@irco.com>