I did an experiment with the DRV8308 EVM and I used the clock frequency mode. The clock frequency is set as 100Hz and the commutation is 180degree sine.
But the LOCKn signal becomes active(low shown as Channel2) when actual FGOUT signal is only 20Hz(shown as Channel 1). It means that the LOCKn signal can become active when the actual frequency does not match Fclkin.
That seems to be conflict with the datasheet.
"Except in PWM input modes, LOCK is also prevented from being signaled if the speed control loop integrator is
saturated (either at 0 or full-scale), which indicates that the speed control loop is not locked." When the FGOUT frequency does not match Fclkin, the integrator should be saturated and the LOCKn should not be active.