Part Number: BOOSTXL-DRV8305EVM
Hi
I am trying to get the over-current protection using CMPSS to work. The system I have is the BOOSTXL-DRV8305EVM connected to a LAUNCHXL-F28379D. I have given the code below. Most of it is based on TI example code. When I run the code, CMPSS1 and 3 are triggered. CMPSS6 is not triggered. When I checked the registers DACHVALS.bit.DACVAL and DACLVALS.bit.DACVAL of CMPSS1 and 3, they have the right values (high value = 0x0D6D, low value = 0x0292). Those compare units have the right values in all other registers as well. However in CMPSS6, all registers are 0. I tried to change those values in the debugger, and they cannot be changed.
1. Why are the CMPSS6 registers are not set to the right values?
2. Why are the CMPSS1 and 3 are triggered?
The current taken by the motor (on the DC link) is about 0.15A and that is nowhere near the limit specified, which is 8A (per phase). Motor runs since I have disabled tripping.
Thanks,
Dhammika
CODE: (Note that HVDMC_Protection() is called during power up init. A1() is called when the system is running)
--------------
//definitions for selecting DACH reference
#define REFERENCE_VDDA 0
//definitions for COMPH input selection
#define NEGIN_DAC 0
#define NEGIN_PIN 1
//definitions for CTRIPH/CTRIPOUTH output selection
#define CTRIP_ASYNCH 0
#define CTRIP_SYNCH 1
#define CTRIP_FILTER 2
#define CTRIP_LATCH 3
void cmpssConfig(volatile struct CMPSS_REGS *v, int16 Hi, int16 Lo)
{
EALLOW;
// Set up COMPCTL register
v->COMPCTL.bit.COMPDACE = 1; // Enable CMPSS
v->COMPCTL.bit.COMPLSOURCE = 0; // Negative signal of the comparator is from internal DAC for COMPL
v->COMPCTL.bit.COMPHSOURCE = 0; // Negative signal of the comparator is from external DAC for COMPH
v->COMPCTL.bit.COMPHINV = 0; // COMP-H output is NOT inverted
v->COMPCTL.bit.COMPLINV = 1; // COMP-L output is inverted
v->COMPCTL.bit.ASYNCHEN = 0; // Disable aynch COMP-H ouput
v->COMPCTL.bit.ASYNCLEN = 0; // Disable aynch COMP-L ouput
v->COMPCTL.bit.CTRIPHSEL = CTRIP_FILTER; // Dig filter output ==> CTRIPH
v->COMPCTL.bit.CTRIPOUTHSEL = CTRIP_FILTER; // Dig filter output ==> CTRIPOUTH
v->COMPCTL.bit.CTRIPLSEL = CTRIP_FILTER; // Dig filter output ==> CTRIPL
v->COMPCTL.bit.CTRIPOUTLSEL = CTRIP_FILTER; // Dig filter output ==> CTRIPOUTL
// Set up COMPHYSCTL register
v->COMPHYSCTL.bit.COMPHYS = 2; // COMP hysteresis set to 2x typical value
// set up COMPDACCTL register
v->COMPDACCTL.bit.SELREF = 0; // VDDA is REF for CMPSS DACs
v->COMPDACCTL.bit.SWLOADSEL = 0; // DAC updated on sysclock
v->COMPDACCTL.bit.DACSOURCE = 0; // Ramp bypassed
EDIS;
// Load DACs - High and Low
v->DACHVALS.bit.DACVAL = Hi; // Set DAC-H to allowed MAX +ve current
v->DACLVALS.bit.DACVAL = Lo; // Set DAC-L to allowed MAX -ve current
EALLOW;
// digital filter settings - HIGH side
v->CTRIPHFILCLKCTL.bit.CLKPRESCALE = clkPrescale; // set time between samples, max : 1023
v->CTRIPHFILCTL.bit.SAMPWIN = sampwin; // # of samples in window, max : 31
v->CTRIPHFILCTL.bit.THRESH = thresh; // recommended : thresh > sampwin/2
v->CTRIPHFILCTL.bit.FILINIT = 1; // Init samples to filter input value
// digital filter settings - LOW side
v->CTRIPLFILCLKCTL.bit.CLKPRESCALE = clkPrescale; // set time between samples, max : 1023
v->CTRIPLFILCTL.bit.SAMPWIN = sampwin; // # of samples in window, max : 31
v->CTRIPLFILCTL.bit.THRESH = thresh; // recommended : thresh > sampwin/2
v->CTRIPLFILCTL.bit.FILINIT = 1; // Init samples to filter input value
// Clear the status register for latched comparator events
v->COMPSTSCLR.bit.HLATCHCLR = 1;
v->COMPSTSCLR.bit.LLATCHCLR = 1;
EDIS;
return;
}
/*********************************************************************
* F28377S is capable of tripping the PWM outputs when overcurrent
* is dtected. It does so without the intervention of the cpu.
* This routine sets up the CMPSS and PWM-xbar
*
*********************************************************************/
void HVDMC_Protection(void)
{
// F28377S 100 pin package has only CMPIN1P, CMPIN2P, CMPIN3P and CMPIN4P
// So, it is better to use the analog inputs ADCINA2, ADCINA4, ADCINB2 and
// ADCIN14 respectively. Terumo circuit may need to be redesigned.
// Configure GPIO used for Trip Mechanism
// ADC inputs are connected to the CMPSS inputs as well.
// Shunt Current phase V(ADCINA2 = CMPIN1P), phase W(ADCINA4 = CMPIN2P) and
// phase U(ADCINB2 = CMPIN3P), High Low Compare event trips
SHUNT_curHi = 2048 + SHUNT(curLimit);
SHUNT_curLo = 2048 - SHUNT(curLimit);
// CMPIN1P is connected to Cmpss1Regs.
// CMPIN2P is connected to Cmpss3Regs.
// CMPIN3P is connected to Cmpss6Regs.
cmpssConfig(&Cmpss1Regs, SHUNT_curHi, SHUNT_curLo); //Enable CMPSS1 - Shunt V
cmpssConfig(&Cmpss3Regs, SHUNT_curHi, SHUNT_curLo); //Enable CMPSS3 - Shunt W
cmpssConfig(&Cmpss6Regs, SHUNT_curHi, SHUNT_curLo); //Enable CMPSS6 - Shunt U
// CMPSS's CTRIPH and CTRIPL outputs are connected to the ePWM-xbar.
// Configure TRIP 4 to OR the High and Low trips from CMPSS comparators 1, 3 & 6.
// Trip 4 is used since that is the first trip signal coming out of ePWM-xbar.
EALLOW;
// Clear everything first
EPwmXbarRegs.TRIP4MUX0TO15CFG.all = 0x0000;
EPwmXbarRegs.TRIP4MUX16TO31CFG.all = 0x0000;
// For CMPSS's (CTRIPL OR CTRIPH) conditions, the muxes used are as follows.
// For CMPSS1.CTRIPH_OR_CTRIPL - mux 0
// For CMPSS2.CTRIPH_OR_CTRIPL - mux 2
// For CMPSS3.CTRIPH_OR_CTRIPL - mux 4
// For CMPSS4.CTRIPH_OR_CTRIPL - mux 6
// For CMPSS5.CTRIPH_OR_CTRIPL - mux 8
// For CMPSS6.CTRIPH_OR_CTRIPL - mux 10
// For all these muxes, the mux control input should be set to 1
// in order to route the signals to Trip4.
// Select the control inputs of the above muxes.
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX10 = 1; //cmpss6 - tripH or tripL
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX4 = 1; //cmpss3 - tripH or tripL
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 1; //cmpss1 - tripH or tripL
// Disable all the muxes first
EPwmXbarRegs.TRIP4MUXENABLE.all = 0x0000;
// Enable Mux 0, 4 and 10 to generate TRIP4 signal.
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX10 = 1;
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX4 = 1;
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1;
// Route the trip signals to GPIO using output xbar
// The following configures only output 1.
// That means all trip signals are ORed and output to
// just one GPIO pin.
OutputXbarRegs.OUTPUT1MUX0TO15CFG.all = 0;
OutputXbarRegs.OUTPUT1MUX16TO31CFG.all = 0;
OutputXbarRegs.OUTPUT1MUXENABLE.all = 0;
// Route the CMPSS1.CTRIPOUTH_OR_CTRIPOUTL
// CMPSS3.CTRIPOUTH_OR_CTRIPOUTL and
// CMPSS6.CTRIPOUTH_OR_CTRIPOUTL to MUX0, 4 and 10 of OutputXbar1
OutputXbarRegs.OUTPUT1MUX0TO15CFG.bit.MUX0 = 1;
OutputXbarRegs.OUTPUT1MUX0TO15CFG.bit.MUX4 = 1;
OutputXbarRegs.OUTPUT1MUX0TO15CFG.bit.MUX10 = 1;
OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX0 = 1;
OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX4 = 1;
OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX10 = 1;
OutputXbarRegs.OUTPUTLATCHENABLE.bit.OUTPUT1 = 1;
OutputXbarRegs.OUTPUTLATCHCLR.bit.OUTPUT1 = 1;
OutputXbarRegs.OUTPUTINV.bit.OUTPUT1 = 0;
// Route OutputXbar1 to GPIO24
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 1; // pull up diabled // in BOOSTXL only
GpioCtrlRegs.GPAGMUX2.bit.GPIO24 = 0;
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO24 = 1;
// Set the ePWM1, ePWM2 and ePWM 3 to be tripped by TRIP4 if there is over-current.
// One-shot mode is used so that PWM outputs will remain low
// once they are tripped.
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3; //Trip 4 is the input to the DCAHCOMPSEL
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI; // 010: DCAH = high, DCAL = don't care
EPwm1Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; // DCAEVT1 Source Signal Select, 0: Source Is DCAEVT1 Signal, 1: Source Is DCEVTFILT Signal
EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; // DCAEVT1 Force Synchronization Signal Select, 0: Source is passed through asynchronously, 1: Source is synchronized with EPWMCLK
EPwm1Regs.TZSEL.bit.DCAEVT1 = 1; // 1/0 - Enable/Disable One Shot Mode.
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3; //Trip 4 is the input to the DCAHCOMPSEL
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI;
EPwm2Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1;
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0;
EPwm2Regs.TZSEL.bit.DCAEVT1 = 1;
EPwm3Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3; //Trip 4 is the input to the DCAHCOMPSEL
EPwm3Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI;
EPwm3Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1;
EPwm3Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0;
EPwm3Regs.TZSEL.bit.DCAEVT1 = 1;
EPwm1Regs.TZSEL.bit.CBC6 = 0x0; // Emulator Stop ? (This is enabling cycle by cycle disablement for TZ6 input
EPwm2Regs.TZSEL.bit.CBC6 = 0x0; // Emulator Stop ? (This is enabling cycle by cycle disablement for TZ6 input
EPwm3Regs.TZSEL.bit.CBC6 = 0x0; // Emulator Stop ? (This is enabling cycle by cycle disablement for TZ6 input
// What do we want the OST/CBC events to do?
// TZA events can force EPWMxA
// TZB events can force EPWMxB
EPwm1Regs.TZCTL.bit.TZA = TZ_NO_CHANGE; //TZ_NO_CHANGE; // TZ_FORCE_LO; // EPWMxA will go low - Dhammika TZ_FORCE_LO
EPwm1Regs.TZCTL.bit.TZB = TZ_NO_CHANGE; //TZ_NO_CHANGE; // TZ_FORCE_LO; // EPWMxB will go low - Dhammika TZ_NO_CHANGE
EPwm2Regs.TZCTL.bit.TZA = TZ_NO_CHANGE; //TZ_NO_CHANGE; // TZ_FORCE_LO; // EPWMxA will go low
EPwm2Regs.TZCTL.bit.TZB = TZ_NO_CHANGE; //TZ_NO_CHANGE; // TZ_FORCE_LO; // EPWMxB will go low
EPwm3Regs.TZCTL.bit.TZA = TZ_NO_CHANGE; //TZ_NO_CHANGE; // TZ_FORCE_LO; // EPWMxA will go low
EPwm3Regs.TZCTL.bit.TZB = TZ_NO_CHANGE; //TZ_NO_CHANGE; // TZ_FORCE_LO; // EPWMxB will go low
// Clear any spurious OV trip
EPwm1Regs.TZCLR.bit.DCAEVT1 = 1;
EPwm2Regs.TZCLR.bit.DCAEVT1 = 1;
EPwm3Regs.TZCLR.bit.DCAEVT1 = 1;
EPwm1Regs.TZCLR.bit.OST = 1;
EPwm2Regs.TZCLR.bit.OST = 1;
EPwm3Regs.TZCLR.bit.OST = 1;
EDIS;
//************************** End of Prot. Conf. ***************************//
}
// Setup OCP (over current protection) limits and digital filter parameters of CMPSS (compare subsystem)
void CMPSS_DIG_FILTER(volatile struct CMPSS_REGS *v, Uint16 curHi, Uint16 curLo)
{
// comparator references
v->DACHVALS.bit.DACVAL = curHi; // positive max current limit
v->DACLVALS.bit.DACVAL = curLo; // negative max current limit
EALLOW;
// digital filter settings - HIGH side
v->CTRIPHFILCLKCTL.bit.CLKPRESCALE = clkPrescale; // set time between samples, max : 1023
v->CTRIPHFILCTL.bit.SAMPWIN = sampwin; // # of samples in window, max : 31
v->CTRIPHFILCTL.bit.THRESH = thresh; // recommended : thresh > sampwin/2
// digital filter settings - LOW side
v->CTRIPLFILCLKCTL.bit.CLKPRESCALE = clkPrescale; // Max count of 1023 */
v->CTRIPLFILCTL.bit.SAMPWIN = sampwin; // # of samples in window, max : 31
v->CTRIPLFILCTL.bit.THRESH = thresh; // recommended : thresh > sampwin/2
EDIS;
return;
}
//--------------------------------------------------------
void A1(void) // SPARE (not used)
//--------------------------------------------------------
{
#if 1
// *******************************************************
// Current limit setting / tuning in Debug environment
//
// Digital filter was set during initilization.
// The following code however will allow those
// values to be changed while running with the debugger.
// This way the current limit can be tuned.
// *******************************************************
SHUNT_curHi = 2048 + SHUNT(curLimit);
SHUNT_curLo = 2048 - SHUNT(curLimit);
CMPSS_DIG_FILTER(&Cmpss1Regs, SHUNT_curHi, SHUNT_curLo); // SHUNT - V
CMPSS_DIG_FILTER(&Cmpss3Regs, SHUNT_curHi, SHUNT_curLo); // SHUNT - W
CMPSS_DIG_FILTER(&Cmpss6Regs, SHUNT_curHi, SHUNT_curLo); // SHUNT - U
//**********************************************************************
// Check if a tripping has occurred. If so, disable the whole inverter.
//**********************************************************************
// Check for PWM trip due to over current
if (EPwm1Regs.TZFLG.bit.OST ||
EPwm2Regs.TZFLG.bit.OST ||
EPwm3Regs.TZFLG.bit.OST
)
{
// if any EPwm's OST is set, force OST on all three to DISABLE inverter
EALLOW;
EPwm1Regs.TZFRC.bit.OST = 1;
EPwm2Regs.TZFRC.bit.OST = 1;
EPwm3Regs.TZFRC.bit.OST = 1;
EDIS;
TripFlagDMC = 1; // Trip on DMC (halt and IPM fault trip )
//RunMotor = 0;
}
//*****************************************************************
// Allow manual clearing of the tripping during debugging
//*****************************************************************
// If clear cmd received, reset PWM trip
if (clearTripFlagDMC)
{
//GpioDataRegs.GPBDAT.bit.GPIO41 = 0; // clear the ocp latch in macro M6. OCP = Over Current Protection
TripFlagDMC = 0; // Trip indicates that over current tripping has occurred. DMC = digital motor control
clearTripFlagDMC = 0;
//GpioDataRegs.GPBDAT.bit.GPIO41 = 1;
// clear EPWM trip flags
DELAY_US(1L);
EALLOW;
// clear OST flags
EPwm1Regs.TZCLR.bit.OST = 1;
EPwm2Regs.TZCLR.bit.OST = 1;
EPwm3Regs.TZCLR.bit.OST = 1;
// clear DCAEVT1 flags
EPwm1Regs.TZCLR.bit.DCAEVT1 = 1;
EPwm2Regs.TZCLR.bit.DCAEVT1 = 1;
EPwm3Regs.TZCLR.bit.DCAEVT1 = 1;
// clear HLATCH - (not in TRIP gen path)
Cmpss1Regs.COMPSTSCLR.bit.HLATCHCLR = 1;
Cmpss3Regs.COMPSTSCLR.bit.HLATCHCLR = 1;
Cmpss6Regs.COMPSTSCLR.bit.HLATCHCLR = 1;
// clear LLATCH - (not in TRIP gen path)
Cmpss1Regs.COMPSTSCLR.bit.LLATCHCLR = 1;
Cmpss3Regs.COMPSTSCLR.bit.LLATCHCLR = 1;
Cmpss6Regs.COMPSTSCLR.bit.LLATCHCLR = 1;
EDIS;
}
#endif
//-------------------
//the next time CpuTimer0 'counter' reaches Period value go to A2
A_Task_Ptr = &A2;
//-------------------
}
