Part Number:DRV8323
Hi,
the datasheet of DRV8323 specs to connect SPA to high side of Rsen and SNA to low side (Figure 14, page 26). However the output SOA is inverse when I do so.
Shouldnt it be the other way around? I think the EVM also has the connection of SPA to low side of Rsen and SNA to high side.
Same applies to current shunt amp B and C.
Secondly in chapter 7.6 SPI timing requirements tclk is specced as 100ns. Is this correct? I thought it was 1 MHz or 1µs.
Rgds Kevin
