TPL7407L - CMOS construction and unuse pin

Hi team

Would you mind if we ask TPL7407?
We are very sorry to keep pestering you again.

<Question1>
On the datasheet  P7, there is functional block diagram. 
(Please visit the site to view this file)
We have question about CMOS.
CMOS composes of two MOSFET(PMOS and NMOS) generally.
So, in this case, are there body diode between Drain and Source in both MOSFETs?

<Question2>
Could you let us know about terminal processing of unuse input pins and output pins?
(it is the same as Logic device, isn't it?)
-Input : GND?
-Output pins : Open?

Kind regards,

Hirotaka Matsumoto