Part Number:DRV8860
I am looking to daisy chain some DRV8860 chips. I have a few questions...
1. Is there a maximum number you can daisy chain?
2. For the timing constraints in section 7.6, the latch to clk time (th) is 1 uS. Is that the delay I need to give it before the clk signal is generated?
3. For the CLK high and low time, it says a minimum of 2.5 uS. Does that mean I can go no slower than 400 Khz on the clk?
4. Are there any timing constraints when daisy chaining?
