DRV8301 requires pulsing nSCS on read commands, despite datasheet.

The DRV8301 datasheet says that "After the 16th clock cycle or when nSCS transitions from LOW to HIGH, the SDI shift register data is transferred into a latch where the input word is decoded."

This leads one to believe that you can simply pull down nSCS once per <read-command, data clock-out> pair of 16 bit transfers, since the first command should be committed after the 16th clock cycle. However, this did not work for me, I had to pulse nSCS high and low again between the read command, and the clock-out of the read data.

Can you please update the datasheet to make this explicit.

Thanks,

Oskar.