DRV10983: Minimum fall/rise time on the SCL/SDA line?

Part Number:DRV10983

Hello,

For a customer of mine I received this question: 

Could you tell me whether there is a minimum fall/rise time on the SCL/SDA line?

They are facing some I2C issues between FPGA used as master and the driver.

When decreasing the current strength of the FPGA outputs on the SCL/SDA lines the problem seems to be fixed.

By doing this the fall time is going from 1.62ns to 7.5ns

Thanks in advance for you help