Part Number:DRV8801
Hi
I'm trying to simulate all details of what happens in our system and find the datasheet does not provide all the information I need.
My question is related to the timings of the MOS FET gates.
I'm dealing with the driver in slow decay mode (MODE 1 pin high)
The datasheet gives an on and off times for the gates 600 ns and 100 ns respectively. It also states a cross over delay tcod which I figure is just On time minus Off time.
With the differences in on and off time, there will be short moments when neither the high or the low gate is on, sort of resembles the free wheel mode, so call it free wheel.
When the high gate is active, call it drive and when low is active call it brake mode.
Now assume the duty cycle gets shorter and shorter.
Examle: at a duty cycle of 600 ns, starting at the PWM (Enable) puls going high
starts out with low gate active and high gate inactive
at 100 ns lower gate gets inactive, so free wheel mode
at 600 ns high gate gets active, drive mode
at 700 ns high gate gets inactive, free wheel mode
at 1200 ns low gate gets active, brake mode
Hence we have only 100 ns of drive mode (and totally 1000 ns of free wheel)
At duty cycle of 500 ns, the drive mode time will be 0 ns.
At lets say 450 ns duty cycle, the drive mode will never kick in, but will there be a free wheel, and for how long?
At a duty cycle shorter than 100ns (Toff), will the high side ever turn off?
I would like to know all the details about this. I would guess the driver internally has some kind of dynamic system that controls the gate states. How does that operate?
Is there a SPICE model of this?
Thanks beforehand
Johan