Part Number:DRV8312
Tool/software: Code Composer Studio
Hi Motor Applications Team,
Since "OT latching shutdown mode is recommended to prevent the channel with low side FET on stuck in Hi-Z during OC event in CBC mode" is described in the data sheet(page 13), I selected the OC latching shutdown mode for 2Q operation. but, the DRVs were latched in the Hi-Z state by the inrush current and I have to reset the DRVs periodically to restore the DRVs.
I tried the CBC current limit mode for 2Q operation. In the case DRVs were not latched in the Hi-Z state and overall drive system works well without periodic reset.
Both of the OC-ADJUST Resistor are 43k ohm..
So, I like to choose CBC mode for 2Q operation, but I want to clearly understand the reason why you recommended OC latching mode instead of CBC.
1. Does "OC event" means the over current during short to power and short to ground conditions?
2. Does "low side FET on stuck in Hi-Z" means FET stays in Hi-Z state, not in turned on state?
3. Is there ways to resolve the problem with the CBC mode?
4. I think the "OC event and stuck in Hi-Z state" also occurs in the complementary operation and CBC mode.
Even if it happen. is it not a problem in the case?
Sincerely
Sewoong KIm.