Part Number:BOOSTXL-DRV8323RS
Hi,
I am reading now DRV832x (SLVSDJ3B) datasheet and would like to ask a question to clarify 1x PWM mode brake mode.
Section 8.3.1.1.3, page 30. The INLC pin, when pulled low enters DRV832x in brake mode by turning off all high-side MOSFETs and turning on all low-side MOSFETs.
Section 8.6.2.1, page 55, Driver control register. Brake mode is entered by setting bit 1 BRAKE to 1. Also it is said there that this bit is ORed with INLC.
It looks like the polarity of INLC pin and BRAKE bit is opposite, regarding OR function. Is the datasheet exact in these two points?
Another point for clarification, section 8,6.2.3, Gate Drive LS Register, CBC bit. There is no explicitly written what happens when CBC is set to 0 and whether it can be set to 0.
Regards,
Ivan