DRV8301: question about DRV8301 charge pump regulator and gate output source/sink current spec

How do we decide what value of Charge Pump Capacitor should be added between pins CP1 and CP2?  I see 0.022uF ( at the voltage rating of PVDD) used in the sample schematic in the datasheet. But I also see places where the datasheet mentions 0.22uF for Ccp 

Does this relate to the current capacity of the charge pump dc-dc used to power the gate drive circuity GVDD? 

Also, i see it says GVDD can deliver 30mA ( but is it total 30mA or 30mA can be drawn out on the GVDD pin), does that number depend on the value of Cap between CP1 and CP2? 

Also, is there a way to change the GVDD value?

I also have a question about the peak current source and sink capability, I can set the peak current capability in the registers through SPI. I see the below in the data sheet. Let's say I am operating at setting 1, then the Isource ( peak) should be 1.7A and Isink(peak) should be 2.3A. is that right? But then how does the number get affected by gate resistance? Is there already some gate resistance inside the DRV8301 on the gate drive output pins that sets these numbers or is it dependant on external gate resistance put in series between the gate drive output pins  and the mosfet gate? 

Also, its little confusing that the Vgs = 2v for source specs and Vgs = 8v for sink specs in the datasheet. How is the peak current ( source / sink) affected by the Vgs of the Mosfet.