DRV8340-Q1: Input logic high current mismatch with calculated

Tool/software:

In DRV8340-Q1 datasheet, for Enable pin, input logic high current (I_lH) is mentioned as 80uA (at 5V input) and pull-down resistance of 60kohms (internal pull-down).

If I calculate pull-down current, it is 83.33uA. Why is it mismatches?  Is it the remaining -3.33uA the bias current of internal op-amp?

If it is the case, if Enable pin is floating with VM > UVLO, will it cause 0.2V(3.33u*60k) across Enable pin?

If not, Why is the mismatch in input logic high current and pulldown resistance. (it is matching with INHx, INLx pins input logic high current and pulldown resistance).

Above queries are w.r.t typical values. 

For maximum input logic high current values, all pin logic high currents are not matching with pull-down resistance. (I_IH_max = 90uA and R_pd_min = 50kohms i.e I_pin = 5/50k = 100uA)

For other gate drivers from TI, this mismatch is not observed in the datasheet like DRV8353.

Please explain the reason behind the pin input logic high current values mentioned in datasheet and calculated current from pulldown resistance.

For both typical values and max values.

Thank you.