Part Number: DRV8251A
Tool/software:
We have a simple although I think unusual application for a DRV8251A. We do not use PWM (either generated internally or externally to the device). We simply generate current pulses in a resistive load of approximately 12 ohms. The pulses have a duration of 1.5 msec and repeat every 1 second. Alternate pulses have opposite polarity. The simplified circuit is as follows:
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The operating sequence is:
1. Initially inputs IN1 and IN2 are at logic 0.
2. The 220uF capacitor is charged to 43 volts in approximately 800 msec from a simple boost converter.
3. The boost converter is switched off.
4. The output pulse is generated by: IN1=1, IN2=0 for 1.5 msec.
Steps 2 to 4 then repeat every 1 second, with alternating polarity of IN1 and IN2 to generate opposite polarity output pulses.
However, during each 1.5 msec output pulse the supply voltage to the device (VM) decreases from 42 volts to approximately 24 volts as the capacitor discharges. VM then rises back to 42 volts in 800 msec as the capacitor is recharged:
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This means that the power supply voltage to the device is not constant during operation. During the period when the bridge is conducting, the supply voltage VM drops from 42 volts to 24 volts in 1.5msec. Obviously, for correct operation to occur, the bridge FETs must fully conduct during this period.
We understand that the DRV8251A is intended for use with a constant supply voltage at the VM pin. However we have conducted extensive testing under these conditions and we believe that the device operates as intended. The output FETs appear to fully conduct (with a slight degradation to the high-side FET conduction), the current sense and protection mechanisms (UVLO, overcurrent and thermal) all appear to operate exactly as specified in the datasheet. We have also conducted tests with more extreme conditions of falling VM (by way of reducing the value of the 220uF capacitor) and the device still appears to operate broadly as specified. This suggests that we have a large margin for performance degradation in our proposed application.
Using the circuit shown above we conducted the following tests.
The maximum expected peak output current (assuming FET Rds(on) = 0R) is 42V / 12R = 3.5A so the current sensing threshold is set to 4.86A (by VREF = 4V and RIPROPI = 470R) to ensure that the device does not chop the output FETs.
We have not disabled the current sensing mechanism because we wish to measure the voltage at the IPROPI pin dynamically with a microcontroller ADC.
Various values of capacitor C were used (although our final application would use 220uF).
Input IN1 is supplied with a non-repetitive pulse from a signal generator.
Input IN2 is connected to GND.
The test procedure was as follows:
1. Scope channel 1: Current measured with a current probe at the 12 ohm output load resistor.
2. Scope channel 2: Voltage across one of the FETs measured using a differential voltage probe for high-side and low-side FETs:
3. Capacitor charged to 42 volts with a bench power supply.
4. The power supply is disconnected.
5. Pulse from a bench pulse generator applied to the input IN1.
6. Traces averaged (within scope) across 8 nominally identical events to kill the noise.
7. Data exported to spreadsheet.
8. FET on resistance calculated for each pair of data points (in spreadsheet).
9. FET voltage, current and resistance graphed in each case.
The noise visible on the calculated results of FET on resistance is due to measurement uncertainties (scope used is Tek TDS3032 with only 9-bit vertical resolution).
We looked at 3 sets of conditions with results as follows:
Case 1. C = 220uF, pulse width = 1.5msec
This is the normal operating condition of our proposed application.
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The low-side FET conduction is ideal. The high-side FET conduction commences at the ideal on resistance but then increases to around 0.27 ohms. This increase is of no consequence in our application. Our guess is that the variation in high-side FET resistance is due to the effect of falling VM upon the internal charge pump mechanism and hence the gate drive of the high-side FET.
Case 2. C = 220uF, pulse width = 20msec
This case uses a much extended pulse duration to allow the operation to be examined at substantially lower bridge supply voltages as the capacitor discharged, than would normally be encountered.
![]()
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The low-side FET performance remains good. The High-side FET performance at first matches that of Case 1 but the on resistance begins to increase further to a maximum value of around 0.32 ohms after about 4 msec. This is well outside our desired pulse length of 1.5 msec and so is of no consequence. However, a FET on resistance of 0.32 ohms would be of no consequence in our application. The FET output pulse terminates at around 6.4 msec due to VM reducing below the UVLO threshold of 4.2V (current is around 330mA due to 4.2V through a total resistance of Rds(on)lo + Rds(on)hi + Rout = 0.32 + 0.25 + 12 = 12.57 ohms). Because the voltage across the 220uF capacitor (electrolytic type) recovers slightly when the discharge current is removed, the UVLO mechanism switches on and off after 6.4 msec with reducing frequency as expected. This is of no consequence in our application (we will never reach the UVLO threshold in normal operation) and so the FET resistance beyond 6.4 msec was not derived or shown in the traces above.
Case 3. C = 55uF, Pulse width = 20msec
This allowed the operation to be examined at substantially higher rates of dV/dt on the bridge power supply than would normally be encountered.
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In this case we can see that the FET on resistance for both FETs increases to around 0.37 ohms before the UVLO threshold is reached at around 1.6 msec. Clearly there is some mechanism which affects the resistance of the low-side FET which was not present in Case 1 and Case 2. However, once again a FET on resistance of 0.37 ohms would be of no significance in our application. In all other respects the device appears to operate correctly.
So..... from our observations we believe that the DRV8251A is probably a really good candidate for use in out proposed application. In addition to the observed performance it is compact, low cost, requires low quiescent current and requires very few additional components all of which are essential for us.
We would be extremely grateful if TI could consider these findings with regard to the internal structure and operation of the device in order to assess the suitability of the DRV8251A in this application (with 220uF capacitor, 12 ohm load and 1.5msec pulse every 1 second).
Thanks in advance.
The operating sequence is:
1. Initially inputs IN1 and IN2 are at logic 0.
2. The 220uF capacitor is charged to 43 volts in approximately 800 msec from a simple boost converter.
3. The boost converter is switched off.
4. The output pulse is generated by: IN1=1, IN2=0 for 1.5 msec.
Steps 2 to 4 then repeat every 1 second, with alternating polarity of IN1 and IN2 to generate opposite polarity output pulses.
However, during each 1.5 msec output pulse the supply voltage to the device (VM) decreases from 42 volts to approximately 24 volts as the capacitor discharges. VM then rises back to 42 volts in 800 msec as the capacitor is recharged:
This means that the power supply voltage to the device is not constant during operation. During the period when the bridge is conducting, the supply voltage VM drops from 42 volts to 24 volts in 1.5msec. Obviously, for correct operation to occur, the bridge FETs must fully conduct during this period.
We understand that the DRV8251A is intended for use with a constant supply voltage at the VM pin. However we have conducted extensive testing under these conditions and we believe that the device operates as intended. The output FETs appear to fully conduct (with a slight degradation to the high-side FET conduction), the current sense and protection mechanisms (UVLO, overcurrent and thermal) all appear to operate exactly as specified in the datasheet. We have also conducted tests with more extreme conditions of falling VM (by way of reducing the value of the 220uF capacitor) and the device still appears to operate broadly as specified. This suggests that we have a large margin for performance degradation in our proposed application.
Using the circuit shown above we conducted the following tests.
The maximum expected peak output current (assuming FET Rds(on) = 0R) is 42V / 12R = 3.5A so the current sensing threshold is set to 4.86A (by VREF = 4V and RIPROPI = 470R) to ensure that the device does not chop the output FETs.
We have not disabled the current sensing mechanism because we wish to measure the voltage at the IPROPI pin dynamically with a microcontroller ADC.
Various values of capacitor C were used (although our final application would use 220uF).
Input IN1 is supplied with a non-repetitive pulse from a signal generator.
Input IN2 is connected to GND.
The test procedure was as follows:
1. Scope channel 1: Current measured with a current probe at the 12 ohm output load resistor.
2. Scope channel 2: Voltage across one of the FETs measured using a differential voltage probe for high-side and low-side FETs:
3. Capacitor charged to 42 volts with a bench power supply.
4. The power supply is disconnected.
5. Pulse from a bench pulse generator applied to the input IN1.
6. Traces averaged (within scope) across 8 nominally identical events to kill the noise.
7. Data exported to spreadsheet.
8. FET on resistance calculated for each pair of data points (in spreadsheet).
9. FET voltage, current and resistance graphed in each case.
The noise visible on the calculated results of FET on resistance is due to measurement uncertainties (scope used is Tek TDS3032 with only 9-bit vertical resolution).
We looked at 3 sets of conditions with results as follows:
Case 1. C = 220uF, pulse width = 1.5msec
This is the normal operating condition of our proposed application.
The low-side FET conduction is ideal. The high-side FET conduction commences at the ideal on resistance but then increases to around 0.27 ohms. This increase is of no consequence in our application. Our guess is that the variation in high-side FET resistance is due to the effect of falling VM upon the internal charge pump mechanism and hence the gate drive of the high-side FET.
Case 2. C = 220uF, pulse width = 20msec
This case uses a much extended pulse duration to allow the operation to be examined at substantially lower bridge supply voltages as the capacitor discharged, than would normally be encountered.
The low-side FET performance remains good. The High-side FET performance at first matches that of Case 1 but the on resistance begins to increase further to a maximum value of around 0.32 ohms after about 4 msec. This is well outside our desired pulse length of 1.5 msec and so is of no consequence. However, a FET on resistance of 0.32 ohms would be of no consequence in our application. The FET output pulse terminates at around 6.4 msec due to VM reducing below the UVLO threshold of 4.2V (current is around 330mA due to 4.2V through a total resistance of Rds(on)lo + Rds(on)hi + Rout = 0.32 + 0.25 + 12 = 12.57 ohms). Because the voltage across the 220uF capacitor (electrolytic type) recovers slightly when the discharge current is removed, the UVLO mechanism switches on and off after 6.4 msec with reducing frequency as expected. This is of no consequence in our application (we will never reach the UVLO threshold in normal operation) and so the FET resistance beyond 6.4 msec was not derived or shown in the traces above.
Case 3. C = 55uF, Pulse width = 20msec
This allowed the operation to be examined at substantially higher rates of dV/dt on the bridge power supply than would normally be encountered.
In this case we can see that the FET on resistance for both FETs increases to around 0.37 ohms before the UVLO threshold is reached at around 1.6 msec. Clearly there is some mechanism which affects the resistance of the low-side FET which was not present in Case 1 and Case 2. However, once again a FET on resistance of 0.37 ohms would be of no significance in our application. In all other respects the device appears to operate correctly.
So..... from our observations we believe that the DRV8251A is probably a really good candidate for use in out proposed application. In addition to the observed performance it is compact, low cost, requires low quiescent current and requires very few additional components all of which are essential for us.
We would be extremely grateful if TI could consider these findings with regard to the internal structure and operation of the device in order to assess the suitability of the DRV8251A in this application (with 220uF capacitor, 12 ohm load and 1.5msec pulse every 1 second).
Thanks in advance.
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