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DRV8350: GHx to SHx absolute max voltage

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Part Number: DRV8350

My design is producing short negative transients on GHx relative to SHx that exceed the absolute maximum in the datasheet (-0.3V). I understand that this rating is to protect the zener diode, but I can't find any information about how much energy this diode can reliably absorb, or anything about the capacitance and reverse recovery of this diode and the gate drive FET body diode(s) in parallel with it to tell if it's conducting at all. Can you provide any more specifics?

More generally, I don't understand how any reasonable design making use of this gate driver can avoid exceeding the -0.3V specification. The state machine only applies I_HOLD while turning off the first FET, which can sink 100 mA (does that even apply below SHx?). If one external FET is being turned off with anything over 100 mA (the minimum setting), it seems like this zener diode or the body diode of the gate drive FET will have to conduct. During the miller plateau (when it happens during turn off, depends on the direction of current in/out of the half bridge), the gate of the external FET being turned off has over 100 mA flowing from the C_gd of the external FET out of it it. This means holding the V_gs of the other external FET at 0V requires pulling the same amount of current out of its C_gd, which is the same amount of current if the external FETs are identical. I_HOLD is insufficient to sink enough current to hold it at 0V, so something else has to conduct. (Actually C_gd varies with V_ds, so it's even worse at the end of the V_ds slew.)

I see several other threads about this question, but I'm unsure how to proceed because none of them state safe maximum ratings that seem achievable.

Here's an example of the voltage near the gate driver (GHx relative to SHx, single ended passive probe with a ground spring, device under test floating on battery power, 500 MHz scope and probe):

This is with 300 mA IDRIVE (all 4), which is slow enough to hit TDRIVE right around the time it turns on the second FET. I'd like to increase the current to switch faster, but that will tend to exceed this absolute maximum rating further, so I'm unsure if that risks damage.

My design uses 2 IPTG014N10NM5 in parallel (12 MOSFETs total for all 3 phases). I've got a 1 ohm gate resistor for each individual FET gate. This example is with 300A flowing into the half bridge in question, so the turn-off of the low side FET commutates to the high-side FET's body diode.


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